Effect of CMOS Technology Scaling on Fully-Integrated Power Supply Efficiency

International audienceIntegrating a power supply in the same die as the powered circuits is an appropriate solution for granular, fine and fast power management. To allow same-die co-integration, fully integrated DC-DC converters designed in the latest CMOS technologies have been greatly studied by academics and industrialists in the last decade. However, there is little study concerning the effects of the CMOS scaling on these particular circuits. To show the trends, this paper compares the achievable efficiencies of the 2:1 switched capacitor DC-DC converter topology under the same constraints in 65, 130 and 350nm bulk CMOS nodes and 28nm in bulk and FDSOI technologies with various capacitor options

3D ICs: An Opportunity for Fully-Integrated, Dense and Efficient Power Supplies

International audienceWith 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm 2 silicon area. An additional high density capacitance layer (100nF/mm 2) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies

Investigation of the power-clock network impact on adiabatic logic

International audienceAdiabatic logic is architecture design style which seems to be a good candidate to reduce the power consumption of digital cores. One key difference is that the power supply is also the clock signal. A lot of work on different adiabatic logic families has been done but the impact of the power supply and the power-clock network still remains to be studied. In this paper, we investigate the power-clock network effect on adiabatic energy dissipation. We derive closed-form analytical formulas to represent the output signal voltage and energy dissipation while taking into account the parasitic impedance of the power-clock network with respect to switching frequency such that adiabatic conditions are still met. Experiments, based on simulation, show that the power-clock network impacts both the energy efficiency of the circuit and its frequency

Design and optimization of power-clock generator and distribution network for adiabatic logic

La densité de puissance est devenue la principale préoccupation lorsqu'un circuit numérique est conçu. Comme pour tous les systèmes embarqués, chaque nouvelle génération de système numérique a plus d'applications que la précédente et exige en fin de compte une plus grande densité de puissance. C'est pourquoi de nombreux chercheurs et concepteurs industriels se sont penchés sur de nouvelles méthodes de réduction de la consommation énergétique des circuits numériques. La logique adiabatique est un style de conception prometteur qui peut réduire la dissipation d'énergie dynamique. La logique adiabatique est différente de la logique conventionnelle en deux principaux points : 1) l’alimentation d’une porte logique adiabatique est un signal à 4 phases, et 2) l’énergie stockée dans la porte est récupérée. Afin de respecter ces principes, la logique adiabatique nécessite une alimentation spéciale. Étant donné que l’objectif d’une telle alimentation est d’agir comme une horloge, elle est appelée alimentation-horloge. L'objectif de cette thèse est de concevoir et d'optimiser une alimentation-horloge ainsi que son réseau de distribution. Cette thèse a été financée par l'Agence Nationale pour la Recherche, ANR, avec le projet ADIANEMS2 (numéro de subvention : ANR-15-CE24-0013).Power density has become the primary concern when a digital core is designed. As in any embedded systems, each new digital core generation has more applications than the previous one and ultimately demands more power density. This is why many researchers and industrial designers have been looking into novel methods for reducing power consumption of digital circuit. Adiabatic logic is a promising design style, which can reduce the dynamic energy dissipation. Adiabatic logic is different than conventional logic in two main points: 1) adiabatic gate are charged with a 4-phase power signal, and 2) the energy, which is stored in the gate, is recovered. In order to fulfill these principles, the adiabatic logic needs a special power supply. As the purpose of such supply is to act as a clock also, it is referred as power-clock supply. The aim of this thesis is to design and optimize a power-clock supply and its delivery network. This thesis has been funded by the French National Research Agency, ANR, with the project ADIANEMS2 (Grant number: ANR-15-CE24-0013)

Conception et optimisation d'une alimentation-horloge et d'un réseau de distribution pour la logique adiabatique

Power density has become the primary concern when a digital core is designed. As in any embedded systems, each new digital core generation has more applications than the previous one and ultimately demands more power density. This is why many researchers and industrial designers have been looking into novel methods for reducing power consumption of digital circuit. Adiabatic logic is a promising design style, which can reduce the dynamic energy dissipation. Adiabatic logic is different than conventional logic in two main points: 1) adiabatic gate are charged with a 4-phase power signal, and 2) the energy, which is stored in the gate, is recovered. In order to fulfill these principles, the adiabatic logic needs a special power supply. As the purpose of such supply is to act as a clock also, it is referred as power-clock supply. The aim of this thesis is to design and optimize a power-clock supply and its delivery network. This thesis has been funded by the French National Research Agency, ANR, with the project ADIANEMS2 (Grant number: ANR-15-CE24-0013).La densité de puissance est devenue la principale préoccupation lorsqu'un circuit numérique est conçu. Comme pour tous les systèmes embarqués, chaque nouvelle génération de système numérique a plus d'applications que la précédente et exige en fin de compte une plus grande densité de puissance. C'est pourquoi de nombreux chercheurs et concepteurs industriels se sont penchés sur de nouvelles méthodes de réduction de la consommation énergétique des circuits numériques. La logique adiabatique est un style de conception prometteur qui peut réduire la dissipation d'énergie dynamique. La logique adiabatique est différente de la logique conventionnelle en deux principaux points : 1) l’alimentation d’une porte logique adiabatique est un signal à 4 phases, et 2) l’énergie stockée dans la porte est récupérée. Afin de respecter ces principes, la logique adiabatique nécessite une alimentation spéciale. Étant donné que l’objectif d’une telle alimentation est d’agir comme une horloge, elle est appelée alimentation-horloge. L'objectif de cette thèse est de concevoir et d'optimiser une alimentation-horloge ainsi que son réseau de distribution. Cette thèse a été financée par l'Agence Nationale pour la Recherche, ANR, avec le projet ADIANEMS2 (numéro de subvention : ANR-15-CE24-0013)

4-Phase Resonant Power-Clock Supply for Adiabatic Logic

National audienc

Synchronised 4-Phase Resonant Power Clock Supply for Energy Efficient Adiabatic Logic

International audienceAdiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply). We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-adiabatic CMOS pipeline

Impact of Power-Clock Network on Adiabatic Logic

National audienc